1. Field of the Invention
The present invention generally relates to an apparatus and a method for plating pin grid array (PGA) packaging modules and, more particularly, relates to an apparatus and method for plating a plurality of pin grid array packaging modules at the same time using a fixture that protects and seals the pinned surfaces of the packaging modules during a plating operation.
2. Description of the Related Art
Pin grid array (PGA) packaging modules, such as those described in U.S. Pat. No. 5,516,416, are commonly used as integrated circuit chip carriers. These PGA packaging modules generally are ceramic packaging modules with cavity die attach and gold wire bonding with PGA contacts. However, another type of ceramic PGA package is a C4 (flipchip) package in which the chip is solder joined directly to the C4 pads (microsockets) on the top surface metallurgy (TSM). Alumina is frequently the ceramic material chosen while molybdenum or tungsten is commonly used in an alumina ceramic substrate as metallic conductors. These PGA packaging modules can include solderable or pluggable type packages. In the manufacturing of PGA packaging modules, after a conventional nickel plating of Mo or W surface features is first performed, pins are brazed onto the I/O pads with Cu-Ag or Ag as the typical brazing material.
In the context of such C4 (flipchip) packages, a need arises for selective plating of the TSM as the C4 pads only require a thin layer of gold, e.g., approximately 300 .ANG., while the pins require about 1 .mu.m of gold. While Au-Sn type pins are known which would eliminate the need for such selective plating, KOVAR type pins that are electrolytically plated with nickel and gold layers are currently favored as they are considerably less expensive pin constructions.
As a consequence, selective plating has become necessary in which the top surface metallurgy (TSM) is immersion gold (Au) plated in one operation, while bottom surface metallurgy (BSM) of the PGA package module is electrolytically plated with nickel and gold layers in separate steps. The TSM is immersion gold plated in the C4 (flipchip) packages because C4 pads are not always connected to the pins where electrical contact is made during electrolytic plating. However, since electrolytic nickel and gold adheres poorly to diffused immersion gold, the industry has tried to eliminate the electroless immersion gold plating film from the pins. As one approach, packaging companies have immersion gold plated both the TSM and the BSM without attempting to protect the BSM during the immersion gold plating process. Thereafter, the TSM is protected while the immersion gold is etched off the pins. The drawback with this approach is that the need for stripping off the gold from the pins in this manner before the nickel and gold electroplating of the pins increases the fabrication cycle time and costs.
Nonetheless, the resort to such stripping of the electroless immersion gold off the pins is not surprising because of several difficulties in masking off BSM during immersion gold plating of TSM. First, because immersion gold plating of the TSM must be performed post braze, the BSM is already a three-dimensional structure at this stage of the process, and it is not a simple task by any means to mask off the three-dimensional array of pins. That is, the backside sealing of PGA packaging modules is complicated due to the sealing area available on the backside of the PGA substrate being limited to a very small area at the peripheral edge while protection must be ensured for the three-dimensional features of the pins themselves. Secondly, the electroless immersion gold bath process is generally performed in an immersion bath of potassium gold cyanide solution at approximately 80.degree. C., and these bath conditions will preclude use of many common masking materials and plating tapes used in the semiconductor industry. Thirdly, the limited space available between the I/O pad center and the substrate edge in many current PGA package modules makes it challenging to provide a fixture which can hold the package in a way that ensures BSM sealing/protection without interfering with TSM gold plating operation. For example, 50 mm.times.50 mm PGA package modules may have an edge of substrate to center of I/O pad spacing of 1.907 mm while 44 mm.times.44 mm PGA package modules may have a substrate edge-to-pad center spacing of only 1.365 mm.
U.S. Pat. No. 5,522,975 (Andricacos et al.) teaches an electroplating workpiece fixture used for electroplating a workpiece having a flat bottom side. Due to the large surface area available on the flat backside of the workpiece, an o-ring is disposed in a complementary groove formed in a holder plateau to seal the flat backside while a vacuum is drawn at a vacuum port located in the holder plateau within the perimeter of the o-ring for drawing the backside of the workpiece against the seal while the opposite front surface of the workpiece is electroplated. While the workpiece is said to take any conventional form requiring uniform plating thickness thereon such as recording heads, packaging modules, or integrated circuits typically used in electronic devices or computers, the flat holder plateau and o-ring seal arrangement would only be structurally compatible with substrates having relatively flat backsides, not three-dimensional backsides such as those encountered in PGA packaging modules. In a somewhat similar vein, U.S. Pat. No. 5,228,966 (Murata) teaches a gilding apparatus including a vacuum chuck used for holding a flat surface of a semiconductor substrate and electrolytically plating the opposite face of the single workpiece.